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Selected Recent Keynote and Plenary Addresses

  1. NanoTec, Design. For Beyond CMOS, Athens (2011) (View PDF)
  2. NanoArch, Computing Inexactly: A Potential Approach to Living with Constraints of Nanoscale, San Francisco (2009) (View PDF)
  3. NSTI Nanotech, Nanostructure Fabrication: Challenges of Top-Down and Bottom-Up Approaches, Boston (2008) (View PDF)
  4. Keck Nanotechnology Symposium, Nanoscale, Science & Engineering & Our Place in the World , (2007) (View PDF)
  5. Society of Hispanic Professional Engineers Nanotechnology Symposium, Nanoscale Science & Engineering: Undergraduate Education & Nanotechnology , (2007) (View PDF)
  6. 25th Microelectronic Engineering Conference, Past 25 Years and the Next 25 years of Electronics: Reality, Dreams, & Engineering in a Changing World (2007) (View PDF)
  7. 20th International Conference on VLSI Design, (2007)
  8. IEEE Nanotechnology Materials and Devices Conference (2006) (View PDF)
  9. SPIE Photonics Europe (2006)
  10. IEEE Conference on Emerging Technologies - Nanoelectronics (2006)

Recent Extended and Short Courses

  1. S. Tiwari (Chair) and Colleagues, Science and Technology of Nanofabrication, NNIN International Winter School for Graduate Students, Bangalore (2010). Content available at at http://www.nnin.org/nnin_iwsg_2010_bangalore.html
  2. S. Tiwari (Chair) and Colleagues, Nanoelectronics with Emphasis on Silicon, NNIN International Winter School for Graduate Students, Mumbai (2009). Content available at http://www.nnin.org/nnin_iwsg_2009_mumbai.html
  3. S. Tiwari (Chair) and Colleagues, Organic Electronics and Optoelectronics, NNIN International Winter School for Graduate Students, Kanpur (2008). Content available at http://www.nnin.org/nnin_iwsg_2008_kanpur.html
  4. S. Tiwari, Silicon Nanoelectronics: From Devices to Systems, IEEE Conference on Emerging Technologies - Nanoelectronics (2006) (View PDF)
  5. S. Tiwari, Devices and Circuits of the Nanoscale, IEEE NMDC (2006) (View PDF)
  6. S. Tiwari, Potential, Characteristics and issues of 3D SOI: 3D-SOI Opportunities, IEEE SOI Conference (2005) (View PDF)

Refereed Publications of Current Interest

  1. E.K. Yu, D. Stewart, S. Tiwari. “Ab-initio Study of Polarization in Graphene Films,” Phys. Rev. B, Vol. 77, 195406 (2008)
  2. A. Gokirmak and S. Tiwari, “Accumulated Body Ultranarrow Channel Silicon Transistor with Extreme Threshold Voltage Tunability,” Appl. Phys. Lett., 91, 243504 (2007)
  3. H. Lin, H. Liu, A. Kumar, U. Avci, J. S. Van Delden and S. Tiwari, ”Strained Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors,” IEEE Electron Device Letters, 28, June, 506 (2007)
  4. S. K. Kim, L. Xue and S. Tiwari, “Low Temperature Three-Dimensional Integration Fabrication Method,” IEEE Electron Device Letters, 28, Aug, 705 (2007)
  5. H. Lin and S. Tiwari, “A Novel Dual Polarity Non-Volatile Memory,” IEEE Electron Device Letters, 28, May, 412 (2007)
  6. H. Lin, H. Liu, A. Kumar, U. Avci, J. S.Van Delden, A. Kumar and S. Tiwari, “Power Adaptive Control of Dense Configured Super-Self-Aligned Back-Gate Planar Transistors, ” International J. of High Speed Electronics and Systems, 17, No. 1, 143-146 (2007)
  7. M. K. Kim, S. D. Chae, C. W. Kim and S. Tiwari, “Non-Volatile High Speed and Low Power Charge Trapping Devices,” International J. of High Speed Electronics and Systems, 17, No. 1, 147-152 (2007)
  8. H. Lin and S. Tiwari, “Localized Charge Trapping due to Adsorption in Nanotube Field-Effect Transistor and its Field-Mediated Transport,” Applied Physics Letters, 89, 073507 (2006)
  9. H. Silva and S. Tiwari, “Random Telegraph Signal in Nanoscale Back-Side Charge Trapping Memories ,” Applied Physics Letters, 88, Mar., 102105 (2006)
  10. H. Lin, H. Liu, A. Kumar, U. Avci, J. S. Van Delden and S. Tiwari, “Super-self-algned back-gate/double-gate planar transistors: Novel Fabrication Approach,” J. Vac. Sc. Technol., B 24 (6), Nov. /Dec., 3230-3233 (2006)
  11. S. Rosenblatt, H. Lin, V. Sazonova, S. Tiwari and P. L. McEuen, “Mixing at 50 GHz using a Single-Walled Carbon Nanotube Transistor,” Applied Physics Letters, 87, Oct., 153111 (2005)
  12. C. C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari, “Bridging the Processor-Memory Performance Gap with 3D IC Technology,” IEEE Design and Test of Computers, Vol. 22, Nov., 556-564 (2005)
  13. A. Gokirmak and S. Tiwari, “Threshold Voltage Tuning and Suppression of Short Channel Effects, Edge Effects and Drain-to-Substrate Leakage in 10 to 30 nm Bulk Fin-Based CMOS Using a Buried Side-Gate,” Electronics Letters, 41, No. 3, 1578-158 (2005)
  14. S. K. Kim, C. C. Liu, L. Xue, and S. Tiwari, “Cross-talk Reduction in Mixed-Signal Three-Dimensional Integrated Circuits with Inter Device Layer Ground-Planes,” IEEE Trans. On Electron Devices, Special Issue on Emerging RF Technologies, 52, No.7, July, 1459- 1467 (2005)
  15. J. A. Wahl, J. Van Delden, and S. Tiwari, “Multiple-Fluorophore-Specie Detection using a Tapered Fabry-Perot Fluorescence Spectrometer,” Applied Optics, 44, No. 9,, 5190-5197 (2005)
  16. U. Avci and S. Tiwari, “A Novel Compact Circuit for 4-PAM Energy-Efficient High Speed Interconnect Data Transmission and Reception,” Microelectronics Journal, 36, No. 1, 67-75 (2005)
  17. M. K. Kim, S. D. Chae, H. S. Chae, J. H. Kim, Y. S. Jeong, H. Silva, S. Tiwari and C.W. Kim, “Ultra-Short SONOS Memories,” IEEE Transactions on Nanotechnology, Dec., 417-424 (2004)
  18. H. Silva and S. Tiwari, “A Nano-Scale Memory and Transistor Using Back-Side Trapping,” IEEE Trans. on Nanotechnology, NT-3, No. 2, 264-269(2004)
  19. U. Avci, A. Kumar and S. Tiwari, “Theoretical and Experimental Analysis of Back-Gated SOI MOSFETs and Back-Floating NVRAMs,” J. of Semiconductor Technology and Science, No. 3, 18-26 (2004)
  20. H. Silva, M.K. Kim, U. Avci, A. Kumar and S. Tiwari, “Non-Volatile Silicon Memories at the Nano-Scale,” Invited Paper, Bulletin of Materials Research Society, Nov., 845-851 (2004)
  21. J. A. Wahl, J. VanDelden and S. Tiwari, “Tapered Fabry-Perot Filters,” IEEE Photonics Technology Letters, 16, No. 8, 1873-1875 (2004)
  22. U. Avci and S. Tiwari, “Nano-Scale Thin Single-Crystal Silicon and its Application to Electronics,” Applied Physics Letters, 84, 13, 2406-2408 (2004)
  23. U. Avci and S. Tiwari, “Back-Gated MOSFETs with Controlled Silicon Thickness MOSFETs for Adaptive Threshold Voltage Control,” Electronics Letters, 40, No. 1, 74-75 (2004)
  24. L. Xue, C. C. Liu, H.-S. Kim, S (K) Kim, and S. Tiwari, “Three-Dimensional Integration: Technology, Use, and Issues for Mixed-Signal Applications,” IEEE Transactions on Electron Devices, 50, No. 3, 601-609 (2003)
  25. A. Kumar and S. Tiwari, “Scaling of Flash NVRAMs to 10's of nm by Decoupling of Storage from Read/Sense using Back-Floating Gates,” IEEE Transactions on Nanotechnology, V1, No. 4, 247 (2002)
  26. C. C. Liu, J. Zhang, A. K. Datta, and S. Tiwari, “Heating Effects of Clock Drivers on Bulk, SOI, and 3D CMOS,” IEEE Electron Device Letters, V23, No.12, 716 (2002)
  27. S. Tiwari, J.A. Wahl, H. Silva, F. Rana and J.J. Welser, “Small Silicon Memories: Confinement, Single-Electron, and Interface State Considerations,” Invited Paper, Applied Physics A 71, 403-414, Oct. (2000)

Conference Publications of Current Interest

  1. M. K. Kim, S. D. Chae, C.W. Kim, J. Kim and S. Tiwari, “Effects of ONO Thickness on Memory Characteristics in NanoScale Charge Trapping Devices,” Tech. Dig. of Int'l Symp on VLSI Technology, Systems and Applications, Hsinchu, (2007)
  2. M. K. Kim, S. D. Chae, C. W. Kim, J. Y. Kim, J-W Lee, and S. Tiwari, “The Effects of the LDD Process on Short Channel Effects in Nano-Scale Charge Trapping Devices,” MRS Spring Meeting (2007)
  3. M. K. Kim, S. D. Chae, C. W. Kim, J-W Lee and S. Tiwari, “A Comparison of n+ and p+ polysilicon gate in High Speed Non-Volatile Memories,” MRS Spring Meeting (2007)
  4. S. Tiwari, A. Kumar, C. C. Liu, H. Lin, S.K. Kim, and H. Silva, “Electronics at Nanoscale: Fundamental and Practical Challenges, and Emerging Directions,” Keynote, , Tech. Dig. of IEEE Conference on Emerging Technologies - Nanoelectronics, Singapore, 1, Jan. (2006)
  5. S. Tiwari, “Energy Constrained Limits to Operation and Assembly of Information Processing Systems: Lessons for Directions of Nanoscale Systems,” Invited Paper, Tech. Dig. of IEEE Nanoscale Materials and Devices Symposium, Oct. 22-25 (2006)
  6. H. Lin, Y.W. Park and S. Tiwari, “A Compact Single Wall Carbon Nanotube Transistor Integrated with Silicon MOSFET Using a Single Common Gate,” MRS Proceedings (2006) Highlighted by Nature Materials
  7. J. Rubin and S. Tiwari, “An Electronic Nonvolatile Memory Device Based On Electrostatic Deflection of a Bistable Mechanical Beam,” MRS Proceedings (2006)
  8. M. K. Kim, S.D. Chae, C.W. Kim and S. Tiwari, “The Effects of the LDD Process on Short-Channel Effects in Nanoscale Charge Trapping Devices,” MRS Proceedings (2006)
  9. A. Gokirmak and S. Tiwari, “CMOS Compatible Integrated Silicon Dioxide Microfluidic Tunnels for Fluidic Sample Delivery to Nanometer Scale Chemical Sensors,” in MRS Proceedings on Micro- and Nanosystems—Materials and Devices, J9.1 (2005)
  10. S. K. Kim, S. Inamdar, S. Tiwari and R. Manohar, “Reduction of Pipeline Mismatches in Three-Dimensionally Integrated (3D) Asynchronous FPGA Circuits,” to appear in Tech. Dig. of IEEE Symposium on Field-Programmable Custom Computing Machines (2005)
  11. S. K. Kim, C. C. Liu, L. Xue and S. Tiwari, “Crosstalk Attenuation with Ground Plane Structures in Three-Dimensionally Integrated Mixed Signal Systems,” Tech. Dig. of IEEE International Microwave Symposium, 2155-2158 (2005)
  12. S. K. Kim and S. Tiwari, “Low Temperature Wafer-Scale 3D ICs: Technology and Characteristics,” Invited Paper, Tech. Digest of International Conf. on IC Design and Technology, May, 183-186(2005)
  13. A. Gokirmak and S. Tiwari, “Integrated Ultra-narrow Silicon Field Effect Transistors with Micro-Fluidic Delivery for Charge Based Sensing,” Invited Paper, Tech. Digest of SPIE - East (2005)
  14. H. Lin and S. Tiwari, “A Novel Nonvolatile Memory Cell for Programmable Logic,” Tech. Dig. of IEEE International SOI Conference, Oct., 208-210(2005)
  15. C. C. Liu and S. Tiwari, “Mapping Multimedia Applications to 3D Systems-on-Chip,” Technical Digest of ISCAS, 2939-2942 (2005)
  16. C.C. Liu, L. Xue, S.K. Kim, I. Ganusov, M. Burtscher and S. Tiwari, “Circuits and Systems Dimensions of 3D Integration,” Invited Paper, Tech. Digest of VLSI Multi-Level Interconnect Conference, Oct. (2005)
  17. M. K. Kim, S.D. Chae, C.W. Kim, J-W Lee and S. Tiwari, “SiO2-SiO2 Charge Trapping Devices,” Tech. Dig. of Semiconductor Interface Specialists Conference, P24, Dec. (2005)
  18. H. Silva and S. Tiwari, “Backside Storage Non-Volatile Memories: Ultra-thin Silicon Layer on a Complex Thin Film Structure,” Ribbon Award Winner, in MRS Proceedings on Materials and Processes for Non-Volatile Memories, 830, D1.4 (2004)
  19. S. K. Kim, L. Xue, and S. Tiwari, “Three-Dimensional Integration with Benzocyclobutene as the Wafer-Bonding Medium,” in MRS Proceedings on Materials, Integration and Packaging Issues for High-Frequency Devices II, 833, G3.5 (2004)
  20. A. Gokirmak and S. Tiwari, “A Silicon Nitride Based Shallow Trench Isolation with Side-Gate for CMOS Integration with MEMS Components for System-On-Chip Applications,” in MRS Proceedings on Materials, Integration and Packaging Issues for High-Frequency Devices II, 833, G6.9 (2004)
  21. S. Tiwari, H. Silva, M. K. Kim, A. Kumar and U. Avci, “Non-Volatile Silicon Memories at the Nanoscale,” Invited Paper, Proceedings of the International Electron Devices and Materials Symposia, 11-14(2004)
  22. A. Kumar and S. Tiwari, “A Power-Performance Adaptive Low Voltage Analog Circuit Design Using Independently Controlled Double Gate CMOS Technology,” Tech. Dig. of IEEE ISCAS, Vol. 1, 197-200 (2004)
  23. A. Kumar and S. Tiwari, “Defect Tolerance for Nanocomputer Architecture,” Tech. Digest of 6'th ACM International Workshop on System Level Interconnect Prediction (SLIP), 89-96(2004)
  24. U. Avci, A. Kumar and S. Tiwari, “Back-gated SOI Technology: Power-Adaptive Logic and Non-Volatile Memory using Identical Processing,” Technical Digest of European Solid State Device Research Conference, 285-288 (2004)
  25. A. Kumar, B. A. Minch and S. Tiwari, “Low Voltage and Performance Tunable CMOS Circuit Design Using Independent Driven Double Gate MOSFETs,” Technical Digest of IEEE International SOI Conference, 119-121 (2004)
  26. U. Avci, A. Kumar, and S. Tiwari, “Back-Floating Gate Non-Volatile Memory,” Technical Digest of IEEE International Silicon on Insulator Conference, 133-135 (2004)
  27. vS. K. Kim, L. Xue, and S. Tiwari, “Low Temperature Silicon Circuit Layering for 3-Dimensional Integration,” Technical Digest of IEEE International Silicon on Insulator Conference, 136-138 (2004)
  28. A. Kumar and S. Tiwari, “Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics,” Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct., 280-288(2004)
  29. M. K. Kim, S.D. Chae, J.H. Kim, S.W. Yoon, Y.S. Jeong, H. Silva, S. Tiwari, and C.W. Kim, “Ultra-Short SONOS Memories,” Technical Digest of IEEE Silicon Nanoelectronics Workshop (2003)
  30. H. Silva and S. Tiwari, “A Scalable Nano-Transistor and Memory using Back-Side Trapping,” Tech. Dig. of IEEE Silicon Nanoelectronics Workshop, (2003)
  31. S. Tiwari, U. Avci, C. C. Liu, L. Xue, A. Kumar, S. Kim and H. Silva, “Are we there yet? Looking beyond the end of scaling in the Nanometer Era,” Invited Paper, Technical Digest of SPIE Conference on Microtechnologies for the New Millenium, V. 5118, 456 (2003)
  32. H. Silva, M. K. Kim, C. W. Kim, and S. Tiwari, “Scaled Front-Side and Back-Side Trapping SONOS Memories on SOI,” Technical Digest of IEEE Silicon on Insulator Conference, 105(2003)
  33. H. Silva, M. K. Kim, A. Kumar, U. Avci, and S. Tiwari, “Few Electron Memories: Finding the Compromise between Performance, Variability and Manufacturability at the NanoScale,” Invited Paper, Technical Digest of International Electron Devices Meeting, 271 (2003)
  34. A. Kumar and S. Tiwari, “Scaling of Flash NVRAMs to 10's of nm by Decoupling of Storage from Read/Sense using Back-Floating Gates,” Technical Digest of IEEE Silicon Nanoelectronics Workshop, 36(2002)
  35. C. C. Liu and S. Tiwari, “Application of 3D CMOS Technology to SRAMs,” Proc. of IEEE Silicon on Insulator Conference, 68(2002)
  36. H. S. Kim, L. Xue, A. Kumar and S. Tiwari, “Fabrication and Electrical Properties of Buried Tungsten Structure for Direct Three-Dimensional Integration,” Proc. of Solid State Devices and Materials Meeting, 98 (2002)
  37. S. Tiwari, H-S Kim, S. Kim, A. Kumar, C. C. Liu, and L. Xue, “Three-Dimensional Integration in Silicon Electronics,” Invited Paper, Proc. of IEEE LFE Conference on High Performance Devices, p.24(2002)
  38. J.A. Wahl, H. Silva, A. Gokirmak, A. Kumar, J.J. Welser and S. Tiwari, “Write, Erase and Storage times in Nano-Crystal Memories and the Role of Interface States and Percolation,” Technical Digest of IEEE International Electron Devices Meeting, Washington p. 375 (1999)
  39. S. Tiwari, “Use of Quantum and Single-Electron Effects in Silicon Memory Structures,” Invited Paper, Government Microcircuit Applications Conference (2000)
  40. A. Kumar, J.J. Welser, S. Tiwari, F. Rana and K. Chan, “Investigations of Silicon Nano-Crystal Floating Gate Memories,” Invited Paper, Technical Digest of Materials Research Society Meeting, Nov. (2000)

Short Conference Abstracts of Current Interest

  1. M.K. Kim, C.W. Kim, J.W. Lee and S. Tiwari, “Multi-bit functional NOR type SONOS Memories,” IEEE Device Research Conference, June (2008)
  2. S. Tiwari, “Nanostructure Fabrication: Challenges of Top-Down and Bottom-Up Approaches,” Invited Paper, NSTI Nanotech 2008, June (2008)
  3. C. Batt, L. Rathbun, A. M. Waldron, A. Mansfield, S. Tiwari and C. Lui, “Communicating Nanoscale Science and Engineering to the General Public,” Invited Paper, OO2.26, MRS Symposium on Lifelong Education in Nanoscience and Engineering , March (2008)
  4. E. Yu, D. Stewart and S. Tiwari, “Ab-Initio Study on Polarization in Graphene Sheets,” American Physical Society March Meeting, Mar. (2008), Based on work that was awarded the first prize in Cornell Undergraduate Research Forum (2007)
  5. H. Lin, Y.W. Park and S. Tiwari, “A Compact Single Wall Carbon Nanotube Transistor Integrated with Silicon MOSFET Using a Single Common Gate,” Tech. Dig. of MRS Fall Meeting, Nov. (2006), a Nature Nanotechnology Highlight.
  6. J. Rubin and S. Tiwari, “An Electronic Nonvolatile Memory Device based on Electrostatic Deflection of a Bistable Mechanical Beam,” Tech. Dig. of MRS Fall Meeting, Nov. (2006)
  7. M. K. Kim, S.D. Chae, C.W. Kim and S. Tiwari, “The Effects of the LDD Process on Short-Channel Effects in Nanoscale Charge Trapping Devices,” Tech. Dig. of MRS Fall Meeting, Nov. (2006)
  8. H. Lin, H. Liu, A. Kumar, U. Avci, J. VanDelden, A. Kumar and S. Tiwari, “ Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors with Thick Source/Drain and Thin Silicon Channel,” Tech. Dig. of IEEE Device Research Conference, June, 37-38(2006)
  9. A. Gokirmak and S. Tiwari, “Accumulated Body MOSFET,” Tech. Dig. of IEEE Device Research Conference, June, 77-78(2006)
  10. H. Lin, H. Liu, A. Kumar, U. Avci, J. S.Van Delden and S. Tiwari, “Power Adaptive Control on Dense Configured Super-Self-Aligned Back-Gate Planar Transistors,” Proc. of IEEE LFE Conference on High Performance Devices (2006)
  11. S. Tiwari, “Complexity, Hierarchy and Energy in Silicon Electronics,” Invited Paper, IEEE LFE Conference on High Performance Devices (2006)
  12. M. K. Kim, S. D. Chae, C. W. Kim and S. Tiwari, “Non-Volatile high Speed and Low Power Charge Trapping Devices,” Proc. of IEEE LFE Conference on High Performance Devices (2006)
  13. M. K. Kim, S. D. Chae, C. W. Kim and S. Tiwari, “A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatible Memories,” Proc. of IEEE LFE Conference on High Performance Devices (2006)
  14. A. Gokirmak and S. Tiwari, “A Side-gated MOSFET: Electrostatic Suppression of Short-channel and Edge Effects for sub-70 nm Gate Length CMOS Technology,” Materials Research Society Symposium, R6.28, Apr. (2006)
  15. A. Gokirmak and S. Tiwari, “Ultra-narrow Width Si FET Integrated with Micro-Fluidic Delivery for Charge Based Sensing,” Materials Research Society Symposium, D4.10, Apr. (2006)
  16. A. Gokirmak and S. Tiwari, “Sub-aF resolution C-V characterization of small-scale MOSFETs,” Materials Research Society Symposium, D3.11, Apr. (2006)
  17. H. Lin, H. Liu, A. Kumar, U. Avci, J. VanDelden, S. Tiwari and A. Kumar, “Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors: A Novel Fabrication Approach,” Tech. Dig. of Int'l Conf. on Electron, Ion and Photon Beam Technology and Nanofabrication, May (2006)
  18. S. Tiwari, C. C. Liu and S. K. Kim, “Device, Circuit and System Dimensions of 3-D Integration,” Invited Paper, Tech. Dig. of IEEE Device Research Conference, June, 33-34(2006)
  19. A. Kumar, S. Mohta, U. E. Avci, A. Kumar and S. Tiwari, “Mobility in Back-Gate/Double-Gate Undoped Thin Silicon Channel Transistors,” Tech. Dig. of IEEE Device Research Conference, June, 35-36(2006)
  20. A. Gokirmak and S. Tiwari, “Integrated Ultra-narrow Silicon Field Effect Transistors with Micro-Fluidic Delivery for Charge Based Sensing,” Invited Paper, Tech. Digest of SPIE - East (2005)
  21. M. K. Kim, S. D. Chae, C. W. Kim, J-W Lee and S. Tiwari, “SiO2-SiO2 Charge Trapping Devices,” Technical Digest of IEEE Semiconductor Interface Specialists Conference, P24 (2005)
  22. S. Tiwari, “NNIN: The National Nanotechnology Infrastructure Network,” Invited Paper, Digest of APS March Meeting, Mar. (2004)
  23. C. C. Liu and S. Tiwari, “Mapping Multimedia Applications to 3D System-on-Chip,” Outstanding Research Presentation Award, Technical Digest of SRC Graduate Fellows Conference (2004)
  24. S.K. Kim, L. Xue and S. Tiwari, “Mixed-Signal Three Dimensional Integration with Benzocyclobutene as
    the Wafer Bonding Medium,” Technical Digest of Materials Society Meeting, Nov. (2004)
  25. A. Gokirmak and S. Tiwari, “A Silicon Nitride Based Shallow Trench Isolation CMOS with Side-gate for Integration with MEMS Components for System-on-Chip Applications,” Technical Digest of Materials Society Meeting, Nov. (2004)
  26. H. Silva and S. Tiwari, “Back-Side Storage Non-Volatile Memories,” Technical Digest of Materials Society Meeting, Nov. (2004)
  27. S. Tiwari, “Nanotechnology: Future Growth Engines,” Invited Paper, Next Generation Growth Engine of Future Industries, Seoul, June (2003)
  28. S. Tiwari, “Nanoelectronics for Massive Integration and Information Processing,” Invited Paper, Korea Conference on Nanotechnology, June (2003)
  29. C. C. Liu and S. Tiwari, “Design of Digital Integrated Circuits for 3D CMOS,” Technical Digest of TechCon (2003)
  30. A. Kumar and S. Tiwari, “Simulation of NVRAMs using Self-Consistent Monte Carlo and its Application to a Back Floating Gate Memory Scalable to 10's of nm,” Technical Digest of TechCon (2003)
  31. S. Tiwari, “The Nano-meters Era: Implications and Speculations for Silicon Electronics,” Invited Paper, Semi-Con South Korea, Jan. (2001)
  32. J. A. Wahl, D. L. Rogers, and S. Tiwari, “High Sensitivity, Low Voltage, Silicon Photodetectors Compatible with Silicon Integration,” IEEE Conference on Lasers and Electrooptics (CLEO), May (2001)
  33. L. Xue and S. Tiwari, “Multi-Layers with Buried Structures (MLBS): An Approach to Three-Dimensional Integration” Technical Digest of IEEE Silicon on Insulator Conference, 12 (2001)
  34. S. Tiwari, “Single Electron Memories: Implications for Technology,” Invited paper, IX'th European Workshop on Dielectrics in Microelectronics, Mar. (1998)
  35. S. Tiwari, P. Solomon, J.J. Welser, E.C. Jones, F.R. McFeely and E. Cartier, “CMOS and Memories: From 100 nm to 10 nm!” Invited paper, International Conference on Micro- and Nanofabrication, Leuven (1998)
  36. S. Tiwari, A. Kumar, J.J. Welser and S. Cohen, “Straddle Gate Transistors: High Ion/Ioff Transistors at Short Gate Lengths,” Technical Digest IEEE Device Research Conference, Charlottesville, June (1999)
  37. J.J. Welser, A. Kumar, T. Furukawa, T.S. Kanarsky, S.J. Holmes, D.V. Horak, N. King, A. Knorr, P.C. Jamison, U. Gruening, C. Radens, J.A. Mandelman, G.B . Bronner, S. Tiwari and M. Hakey,“Deep-Trench Capacitor DRAM Cell Utilizing a Vertical Transistor Sidewall Transfer Device,” IEEE Device Research Conference, Charlottesville, June (1999)
  38. J.J. Welser, S. Tiwari, F. Rana, A. Kumar and K. Chan, “Investigations of Silicon Nano-Crystal Floating Gate Memories,” Invited paper, CREST- Japan Workshop on Future Electron Devices, Kyoto, Sep. (1999)
  39. S. Tiwari, “Nano-Crystal and Quantum-Dot Memories: Implications of Small Dimensions, Quantum Confinement and Interface States,” Invited paper, Technical Digest of American Vacuum Society, Seattle, Oct. (1999)
  40. S. Tiwari, “The Nano-Meters Era: Implications and Speculations for Silicon Electronics,” SEMI-S. Korea, Invited paper, Jan. (2000)
  41. S. Tiwari, “Electronics Using Single-Electron Effects,” Invited paper, Technical Digest of American Vacuum Society, San Francisco, Nov. (2001)
  42. S, Tiwari, “Are We There Yet? Looking Beyond the End of Scaling,” Technical Digest of International Symposium on NT-BT-IT Fusion Technology,” Oct. 21, Seoul (2002)
  43. C. C. Liu and S. Tiwari, “SRAMS in 3D,” Technical Digest of TechCon (2002)
  44. A. Gokirmak and S. Tiwari, “Electronic Gain Cell for Identification of Large Molecules,” Digest of APS March Meeting, N8.008 (2003)
  45. H. Silva and S. Tiwari, “Study of Defects and Interface States in Silicon Memories,” APS Digest of March Meeting, A24.003 (2003)
  46. H. Silva and S. Tiwari, “A Novel Silicon-Based Transistor-Memory Device,” Digest of APS March Meeting, N8.009 (2003)
  47. S. Tiwari, “Silicon Electronics at the Nanoscale: Devices, Technology, Circuits and Architecture,” Invited Paper, Digest of Nano-7 and ECOSS-21, 155(2002)

Patents of Current Interest

  1. 7,365,398 Compact SRAMs and Other Multiple Transistor Structures (Issued 4/29/2008)
  2. 7,057,234 Scalable Nano-Transistor and Memory Using Back-Side Trapping (Issued 6/6/2006)
  3. 6,953,958 Electronic Gain Cell Based Charge Sensor (Issued 10/11/2005)
  4. 6,756,257 Patterned SOI regions on Semiconductor Chips (Issued 6/29/2004)
  5. 6,750,471 Molecular Memory and Logic (Issued 6/15/2004)
  6. 6,600,173 Low temperature semiconductor layering and three-dimensional electronic circuits using the layering (Issued 7/29/2003)
  7. 6,534,819 Dense Backplane Cell for Configurable Logic (Issued 3/18/2003)
  8. 6,350,321 UHV Horizontal Hot Wall Cluster CVD/Growth Design (Issued 2/26/2002)
  9. 6,445,032 Floating Back Gate Electrically Erasable Programmable Read-Only Memory (EEPROM) (Issued 9/3/2002)
  10. 6,472,705 Molecular Memory and Logic (Issued 10/29/2002)
  11. 6,177,289 Lateral trench optical detectors (Issued 2/23/2001)
  12. 6,236,060 Light emitting structures in back-end of line silicon technology (Issued 5/22/2001)
  13. 6,248,626 Floating Back Gate Electrically Erasable Programmable Read-Only Memory (EEPROM) (Issued 6/19/2001)
  14. 6,281,551 Back-Plane for Semiconductor Device (Issued 8/28/2001)
  15. 6,316,309 Method of Forming Self-Isolated and Self-Aligned 4F-Square Vertical FET-Trench DRAM Cells (Issued 11/13/2001)
  16. 6.333,532 Patterned SOI regions in Semiconductor Chips (Issued 12/25/2001)